1. Field of the Invention
The invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of Related Art
A semiconductor device is provided with a passivation film for protecting a semiconductor element. In this semiconductor device, the passivation film may be formed on a boundary where an insulating film contacts an electrode. For example, the electrode may be formed on the insulating film, and the passivation film may be formed extending from the electrode to the insulating film. In such a case, the passivation film is formed on the boundary where the insulating film contacts the electrode. With a semiconductor device having this kind of structure, a crack may form in the passivation film of the boundary portion where the insulating film contacts the electrode, due to a change in external temperature. That is, a large stress may be applied to the passivation film of the boundary portion, such that cracking occurs, due to thermal stress caused by a difference in linear expansion coefficients of the insulating film and the electrode. Therefore, Japanese Patent Application Publication No. 2004-119415 (JP 2004-119415 A) describes technology for preventing the occurrence of cracking in the passivation film due to a change in temperature.
With the technology described in JP 2004-119415 A, a lead wire is formed by an electrode wire of a lower layer, from among electrode wires of multiple layers. Accordingly, the occurrence of shearing stress in a wire upper portion of the uppermost layer due to thermal stress is reduced, so the occurrence of cracking in the passivation film is inhibited. In addition to this, the orientation of the lead wire that is pulled out from the electrode wires is an orientation that is opposite a corner that is closest to a semiconductor chip peripheral edge. As a result, the occurrence of cracking in the passivation film at the corner with the electrode wires and the like is inhibited.
In JP 2004-119415 A, the lead wire forms the electrode wire of a layer that is lower than the uppermost layer. Also, the lead wire is oriented opposite the closest corner. Therefore, the location where the lead wire is able to be formed ends up being limited, so the degree of freedom in design of the semiconductor device decreases.